1. Field of the Invention
Example embodiments of the present invention relate to a method of forming a thin layer structure and more particularly, to a single crystalline thin layer structure and method of forming the same.
2. Description of the Related Art
Conventionally, solid materials may be classified into single-crystal material, poly-crystal material and amorphous material according to a crystal structure thereof. A single crystal material has a unit crystal structure having a regular arrangement, and in contrast, the poly-crystal material has a plurality of unit crystal structures having an irregular and/or random arrangement. An amorphous material has no crystal structure, and atoms may be irregularly and/or randomly arranged in the amorphous material.
A poly-crystal material generally contains a plurality of grain boundaries in the material due a plurality of unit crystal structures, each of which may be aligned in different directions, and carriers such as electrons and holes may be hindered from moving and/or being controlled in the material due to the plurality of grain boundaries, thereby deteriorating electric characteristics of the poly-crystal material. In contrast, a single-crystal material has almost no grain boundaries due to the single-crystal structure of the single-crystal material. Accordingly, carriers may move relatively freely and may be more controllable in a single crystal material than in a poly-crystal material. As a result, electric characteristics of a single-crystal material may be considered superior to that of a poly-crystal material.
In light of the above, a semiconductor device having a stacked structure such as a thin-film transistor (TFT) or having a multilayer structure such as a system-on-chip (SOC) device may include at least one single-crystal thin layer as a channel layer for the semiconductor device.
An amorphous silicon layer may be formed on a seed layer comprising single-crystalline silicon and a crystal structure of the amorphous silicon layer may be transformed into a single-crystal structure using a heat treatment to form a single-crystalline silicon layer.
Alternatively, a single-crystalline silicon layer may be formed by a damascene process. A selective epitaxial growth (SEG) process may be performed in an opening through which a seed layer comprising single-crystalline silicon may be partially exposed until the single-crystalline silicon is grown to a top portion of the opening, thereby forming a single-crystalline silicon layer in the opening. An SEG process may have long processing times and high processing costs, but may result in fewer processing defects and an improved channel layer.
FIG. 1 is a photograph taken by a transmission electron microscope (TEM) of a single crystalline silicon layer formed by a conventional damascene process.
As shown in FIG. 1, according to the conventional damascene process, a silicon oxide fence 16 is created on a seed layer pattern 10 around sidewalls of an opening 12. The seed pattern 10 may be over-etched in forming the opening 12 to sufficiently expose the seed pattern 10 through the opening 12. However, because the seed pattern 10 may be inclined, a small amount of etching gas may be supplied to the seed pattern 10 around the sidewalls of the opening 12, which may form a silicon oxide fence 16 on a seed layer pattern 10 around sidewalls of the opening 12.
A silicon oxide fence 16 may prevent the silicon in the seed pattern 10 from growing so the single crystalline silicon layer 14 locally formed may have a smaller thickness at a bottom portion around the seed pattern 10. For example, the single crystalline silicon layer formed may not be as thick at a portion around the seed pattern 10 due to the silicon oxide fence 16.
If the single crystalline silicon layer is thinner around the seed pattern 10, the ability of carriers to freely move may be reduced, thereby reducing an operating speed of a semiconductor device including the non-uniform single crystalline silicon layer. Further, the smaller thickness of the single crystalline silicon layer around the seed pattern 10 may result in a reduced contact area between the single crystalline silicon layer and the contact plug, thereby increasing an electrical resistance of the contact plug.